1. Field of the Invention
The invention is related to methods of manufacturing semiconductor devices. Particularly, the invention is related to dual work function semiconductor devices having a gate stack comprising high-k materials and a single metal gate electrode.
2. Description of the Related Technology
Scaling MOSFET's to improve performance lead to higher gate leakage as the SiO2 gate dielectric becomes thinner. To address this issue, SiO2 gate dielectric has been replaced with high-k materials (e.g. Hf-based or Al-based material with a dielectric constant k>kSiO2). With the introduction of the high-k materials a new problem aroused, namely the Fermi level pinning effect, originating in the interaction between high-k material and polysilicon. Fermi level pinning is a fundamental characteristic of the polysilicon (polySi)/metal oxide interface that causes high threshold voltages in MOSFET devices.
A known solution to this problem is the introduction of metal gate materials. However, it has been proven difficult to identify band-edge metals (metals with either a n-type or a p-type work function (WF), required for low threshold voltage, V1) that are compatible with the conventional CMOS fabrication process. CMOS can be made using dual metal gates with single or dual dielectrics. In either case, a selective removal of one of the metal gates is necessary and adds substantial complexity and costs to the manufacturing process.
Another known solution for CMOS manufacturing is to use Fully Silicided (FUSI) gate, without a selective removal of electrode or gate dielectric. However, in this approach, FUSI gates require different silicide phases on nMOS and pMOS. On small devices, the phase or composition of the FUSI gates tends to distribute unevenly, resulting in severe within-wafer threshold voltage (Vt) non-uniformity.